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Serial Host Interface SPI Protocol Timing
Table 20. Serial Host Interface SPI Protocol Timing (continued)
No.
34
Characteristics 1,3,4
SCK edge to data out not valid
Mode
Master/Slave
Expressions
2.0 x T C
Min
12.0
Max
—
Unit
ns
(data out hold time)
35
SS assertion to data out valid
Slave
—
—
15.0
ns
(CPHA = 0)
36
37
First SCK sampling edge to HREQ output deassertion
Last SCK sampling edge to HREQ output not
Slave
Slave
3.0 x T C + 30
4.0 x T C
50
52.2
—
—
ns
ns
deasserted (CPHA = 1)
38
SS deassertion to HREQ output not deasserted
Slave
3.0 x T C + 30
46.6
—
ns
(CPHA = 0)
39
40
SS deassertion pulse width (CPHA = 0)
HREQ in assertion to first SCK edge
Slave
Master
2.0 x T C
0.5 x T SPICC + 3.0
12.7
63.0
—
—
ns
ns
x T C + 5
41
HREQ in deassertion to last SCK sampling edge
Master
—
0
—
ns
(HREQ in set-up time) (CPHA = 1)
42
First SCK edge to HREQ in not asserted
Master
—
0
—
ns
(HREQ in hold time)
43
HREQ assertion width
Master
3.0 x T C
20.0
ns
Note:
42
1.
2.
3.
4.
5.
V CORE_VDD = 1.2 5 ± 0.05 V; T J = –40°C to 115°C for 150 MHz; T J = 0°C to 100°C for 181 MHz; C L = 50 pF
Periodically sampled, not 100% tested
All times assume noise free inputs
All times assume internal clock frequency of 150 MHz
Equation applies when the result is positive T C
Figure 9. SPI Master Timing (CPHA = 0)
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
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